The is a high-performance, low-power, low-voltage, Si-gate CMOS devices and superior to most advanced CMOS compatible TTL families.
 
74LVC2G00; Dual 2-input NAND gate
Block diagram of 74LVC2G00DP
74LVC2G02; Dual 2-input NOR gate  Block diagram of 74LVC2G02DC
74LVC2G04; Dual inverter 
74LVC2G08; Dual 2-input AND gate Block diagram of 74LVC2G08DP
74LVC2G14; Dual inverting Schmitt-trigger with 5 V tolerant input  Block diagram of 74LVC2G14GW
74LVC2G32; Dual 2-input OR gate Block diagram of 74LVC2G32DP
74LVC2G86; Dual 2-input exclusive-OR gate Block diagram of 74LVC2G86DP
74LVC2G125; Dual bus buffer/line driver; 3-state Block diagram of 74LVC2G125DP
74LVC2G126; Dual bus buffer/line driver; 3-state Block diagram of 74LVC2G126DP

 


 
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